Experts -
For a DDR3 interface, for an SOC from a vendor that you all have heard
of, we are being advised to:
a)      Reference all DDR3 signals to GND
b)      Terminate certain signals at the far end, to VTT (0.75V)
c)       Make sure the VTT supply can sink and source current
d)      Bypass the VTT supply with caps from VTT to VDD (1.5V) (and not
to GND)
Does item d) make sense, if the signals are GND referenced?  Wouldn't it
make more sense if those signals we referenced against VDD?

The vendor's rationale for bypassing with caps from VTT to VDD is quoted
as follows:
"The reason for bypassing to 1.5V instead of GND is that VTT is both
sinking and sourcing current. When high side mosfet of the buffer is
turned ON, for logic HI, the current flow is from 1.5V to MOSFET to
termination resistor to VTT power supply. Signal is switched referenced
to VTT, so we need to decouple the buffer's 1.5V pin to VTT, not to GND.
No need for the decap between buffer's GND to VTT, because GND is much
more robust than 1.5V rail (usually a massive plain) and can supply
necessary instantaneous current for logic LOW."

What do you think?

Thanks, Stefan M.




d) makes sense if you are also routing according to the recommendations, 
which runs A/C against VDD in the PCB.

Steve

But they are not against VDD, they are against GND. Hence my question; are we 
getting conflicting advice from the vendor (route signals against GND but 
bypass VTT to VDD)

On Sep 7, 2012, at 10:55 PM, "steve weir" <weirsi@xxxxxxxxxx> wrote:


This was recently discussed on si-list in a very detailed way:
http://www.freelists.org/post/si-list/Vref-DQ-Vref-CA-VTT-decoupling-in-DDR3-DIMM
On the bottom of the page you can browse the different posts in the topic.
By the way, I think you are getting conflicting advice. Decouple to used 
reference would make more sense.

regards,
Istvan Nagy
Fortinet


Data signals are supposed to run against GND.  A/C are supposed to run 
against VDD.

Steve


According to whom, or to what spec? This is not an SO-DIMM situation, it is 
memory down, next to the SOC.

On Sep 8, 2012, at 4:37 PM, "steve weir" <weirsi@xxxxxxxxxx> wrote:

And the SOC vendor says all memory signals (including A/C) should be GND 
referenced. But same vendor's FAE says VTT bypass should be to 1.5V. Hence the 
question to this august list.

On Sep 8, 2012, at 6:15 PM, "Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx> 


The JEDEC spec for referencing A/C to 1.5V relates to DIMMs only, AFAIK. The 
A/C signals on the edge connector are nearest the 1.5V fingers and the A/C 
traces are referenced to 1.5V planes on the DIMM PCB. 
As for VTT, I'm not familiar with the advice of decoupling to Vdd rather than 
to GND, but if the PDN has a low enough impedance across the relevant 
frequencies, I'm not sure it will matter. I'd love to be enlightened, though.  

-- 
Don Nelson
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)


Yes, which gives anyone who doesn't want to create headaches for 
themselves and / or their customers a strong incentive to reference A/C 
within their packages to VDD.

Steve.



Then you need to find out what the A/C lines are referenced to in the 
controller.  If the designers were smart, they referenced VDD.  If not, 
reference what they did in the package and apply appropriate bypass at 
the DRAM end.

Steve.


The signal arrives at the termination resistors (or the DRAM) in the form
of an electromagnetic wave.  Do the E and B fields really store any
information about which MOSFET generated them and which power supply it was
connected to?  I don't think so.  In this argument, I don't think the
driving MOSFETs matter at all so long as the IO circuits are sufficiently
decoupled on chip.

If it were me, I'd decouple VTT to GND because that's the reference plane,
but I don't have any lab data to support that.  In fact, I haven't seen
many papers that show lab data for a real-life return current discontinuity
(I hate the phrase).  Maybe it's better just to call it what it is:  a
transmission line reference discontinuity.


"The reason for bypassing to 1.5V instead of GND is that VTT is both
sinking and sourcing current. When high side mosfet of the buffer is
turned ON, for logic HI, the current flow is from 1.5V to MOSFET to
termination resistor to VTT power supply. Signal is switched referenced
to VTT, so we need to decouple the buffer's 1.5V pin to VTT, not to GND.

No need for the decap between buffer's GND to VTT, because GND is much
more robust than 1.5V rail (usually a massive plain) and can supply
necessary instantaneous current for logic LOW."

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901


Hello all,

I'm a bit late to jump into the discussion, and I can anyhow only repeat
what I mentioned last time:

I do not like the idea of a solid ground plane and a weak supply plane.
The only thing that matters  from a voltage point of view is the
difference between them. So I try to treat them equally.
A rock solid GND does not help if the VDD is having the noise.


Additionally one often does not know the used referencing of all
contributors (which seems the case in this discussion). Especially for
DRAMs with mid level termination both current return rails matters. So I
still stay with the target to have GND and VDD treated with the same
care, and if I don't know the whole current return I implement a
symmetrical decoupling.


Hermann


Hi OP
I want to second Herman. I agree GND & VDDQ should treated same
I ALWAYS bypass VTT to GND & VDDQ 

Regards
Farooq Bhatti
Hi Stefan
This is my first post. :-)
I have the similiar case as you. If you are talking about the vtt of DDR3 
fly-by termination.
The ASIC is not planned to support DIMM. So in the package and board design, we 
use ground reference.
After discussion, we change decap to ground now which is the reference or 
return path of the signals.

but I don't think adding both vtt/ground decap and vtt/vdd decap is always good 
idea. it depends.
for example, in the following sencario,it is not a good idea.
1) vtt and vdd are both ground reference or neighbor.
2) signals are ground reference as well. 

in this case, decap between vtt and ground is the choice, but not decap between 
vtt and vdd.
the cap between vtt and vdd will be a way or bridge to inject noise from vtt  
rail to power vdd rail.
in another word, any noise between vtt and ground will be injected to vdd and 
ground because of the bridge casued by cap between vtt and vdd.

the situation will be worse if you don't have enough cap between vdd and ground 
near the cap between vtt and vdd.

you will see high crosstalk. It will be the worst, if the component is located 
at the resonance peak of the Vdd/ground cavity.

So if you don't want strong coupling, then don't add any cap between them.
If you want strong coupling, then add the cap "properly" between them.
But how do we know whether strong coupling is needed or not?
the answer is "it depends".......

by the way, when you connect the signal in the inner layer with the Rtt in the 
external layer, you need a signal via. don't forget place a reference via near 
the signal via. otherwise, you will see the crosstalk. we usually pay attention 
to the signal via in the middle of the trace. but sometimes omit the signal via 
near the termination.

 
Thanks
Feng


I agree: Don't just throw capacitors at a problem. Get the right 
information and design the channel properly with a contiguous reference 
from end to end.

The reasoning behind Vdd reference for A/C has long been that 
substantial Vdd polygons are a necessity, and this allows them to be 
used as returns thus reducing board layer count. If as an industry we 
remain disciplined, we will retain the same references in the die as on 
the PCB. An ASIC may not be designed to go in a DIMM, but the DRAMs 
themselves better be.

Steve.


Stefan,
Are SDRAMs placed on the board with SoC or on a DIMM? Is this a registered
or unbuffered DDR3? The info you provided is insufficient to answer the
question.

Regards,
Vadim
On Sun, Sep 9, 2012 at 3:36 PM, Stefan Milnor