DDR3 Signal Quality & Timing Analysis

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Source: Time:2014/9/10
DDR3 Signal Quality & Timing Analysis - Probe Location at DRAM - Pin or Die?
Q1
Hello everyone,
My observations from the simulation results of a DDR3 interface (64 bit + 8 bit ECC) with five Micron DRAMs:
In FAST corner, when CLK is probed at PIN of first DRAM in the daisy chain, it has good signal quality (monotonic, no DC/Vref multi-crossing). But if it is probed at DIE of the same DRAM, CLK is non-monotonic, multi-crosses DC and Vref thresholds. Signal Quality improves at die of the other DRAMs as we progress down the daisy chain, since the stub length between respective DRAMs and termination decreases.
Give your thoughts to improve the signal quality at first DRAM's die. Currently, the output impedance of DDR3 Controller is set to 40ohms, which is the maximum O/P impedance it supports.
Thanks,
Pugazharasan Selvanathan
Member Technical Staff - Design Centric Services
HCL Technologies Ltd.

A1
Hello,
the flyby CA bus on DDR3 needs careful optimization. Each DRAM is causing a little bit of reflections, and in worst case these overly on one DRAM position. What I find interesting: Often the wave shape at the die is better than at the pin ...
Nevertheless here what is possible:
- Optimize the loaded transmission line part between the DRAMs. This is dependent on the distances between the DRAMs, the corresponding impedances (maybe even two different between the devices) and the input capacitance of the DRAMS.
- Optimize the lead in Length of the Clock: if you have bad luck it is an reflection of the controller that hits you at the first DRAM
- Optimize the length of low and high impedance routing (in the Lead In, and maybe even between the DRAMs).
- Optimize the clock termination at the end (length and value)
- minimize the stub length going go each DRAM component.
- Change the via arrangement for the clock
The improvement down the line is not really because the length to the termination decreases. Dependent on the Layout/design it is possible that each of the DRAMs along the bus can see the worst case of overlay of any reflections. Nevertheless often it is the first one which is getting the worst case.
So I guess all I can tell is, that the design of the DDR3 Flyby bus is difficult and needs to be done very carefully. We have done some designs just by copy an existing Design to a new environment, but this is dangerous ..
So best what you can do is to take your simulator and check what you can change to optimize the SI ...
Best regards
Hermann

A2
Yep, that is true Hermann. 
Also add if u can insert parallel termination near the first device. That is not limitted only to resistive term it can be capacitive term to improve SQ @ first device.


A3
Hello Steve,
Thanks for your guidance. Our DDR3 interface do not use DIMM and have all SDRAMs on the main board itself. On comparing the clock design with "DDR3 SDRAM unbuffered  DIMM Design Specification 1.03", I found discrepancies in Ccomp and Rtt values. 
Parameter       - Current       - Recommended
Ccomp           - 3.3pF - 2.2pF
Rtt             - 49.9ohm       - 36ohm
However, the intra-pair length matching is properly done in layout in accordance with JEDEC specification.

A4
Hello Hermann,
Thanks for your ideas. I absolutely agree with all your points. 
I simulated with different end termination values for DDR3 clock. Currently the parallel termination value is set at 49.9 ohms. Reducing the termination value improves the signal quality at all DRAMs, even at die. However, I will do careful analysis in obtaining good clock signal at all DRAMs. 
Like you said, fly-by topology requires careful optimization, simulation and verification.
Thanks,
Pugazh